DDR1 Synchronous DRAM

Alliance Memory DDR1 Synchronous DRAM is a high-speed CMOS double data rate synchronous DRAM. It is internally configured with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and CK. Read and write accesses to the SDRAM are burst oriented. The Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command.

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Multipla: 1 000
Papprulle: 1 000

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Ledtid för icke lagerfört 8 Veckor
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Multipla: 2 500
Papprulle: 2 500

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Datablad
Ledtid för icke lagerfört 6 Veckor
Min.: 1 000
Multipla: 1 000
Papprulle: 1 000

SDRAM - DDR 512 Mbit 16 bit 200 MHz TSOP-II-66 32 M x 16 700 ps 2.3 V 2.7 V - 40 C + 85 C AS4C32M16D1A Reel