AS4C128M8D3LB-12BCNTR

Alliance Memory
913-4C1288D3LB12BCNT
AS4C128M8D3LB-12BCNTR

Tillverk:

Beskrivning:
DRAM 1G 1.35V 800MHz 128Mx8 DDR3 E-Temp

ECAD-modell:
Ladda ned den kostnadsfria Libary Loader för att omvandla denna fil för ditt ECAD-verktyg. Läs mer om ECAD-modellen.

Tillgänglighet

Lager:
Ej på lager
Fabrikens ledtid:
8 Veckor Uppskattad tillverkningstid i fabriken.
Minst: 2500   Flera: 2500
Enhetspris:
-,-- kr
Ext. pris:
-,-- kr
Est. Pris:
Denna produkt levereras UTAN KOSTNAD

Prissättning (SEK)

Antal Enhetspris
Ext. pris
Komplett Papprulle (beställ i multiplar av 2500)
89,89 kr 224 725,00 kr

Alternativ förpackning

Tillverk: Artikelnummer:
Emballage:
Tray
Tillgänglighet:
På lager
Pris:
128,68 kr
Min:
1

Produktattribut Attributvärde Välj attribut
Alliance Memory
Produktkategori: DRAM
RoHS-direktivet:  
SDRAM - DDR3L
1 Gbit
8 bit
800 MHz
FBGA-78
128 M x 8
225 ps
1.283 V
1.45 V
0 C
+ 95 C
AS4C128M8D3LB
Reel
Märke: Alliance Memory
Monteringsland: TW
Distributionsland: TW
Ursprungsland: TW
Fuktkänsliga: Yes
Monteringsstil: SMD/SMT
Produkttyp: DRAM
Fabriksförpackningskvantitet: 2500
Underkategori: Memory & Data Storage
Strömstyrka - Max: 72 mA
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Attribut som valts: 0

CAHTS:
8542320020
USHTS:
8542320032
MXHTS:
8542320201
ECCN:
EAR99

DDR3 Synchronous DRAM

Alliance Memory DDR3 Synchronous DRAM (SDRAM) achieves high-speed double-data-rate transfer rates of up to 1600Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3 DRAM key features, and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pairs in a source synchronous fashion. These Alliance Memory devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages.

DDR3L SDRAM

Alliance Memory DDR3L SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface that transfers two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. Alliance Memory DDR3L SDRAM is available in various package sizes.