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Texas Instruments ADC12QJ1600-SP Quad Channel ADC

Texas Instruments ADC12QJ1600-SP Quad Channel Analog-to-Digital Converter (ADC) features 12-bit resolution, a high sampling rate (1.6GSPS maximum), and low power consumption, making it ideal for a variety of multi-channel communications systems. The full-power input bandwidth (-3dB) of 6GHz allows direct RF sampling of the L-band and S-band. The ADC12QJ1600-SP includes clocking features to relax system hardware requirements, such as an internal phase-locked loop (PLL) with an integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs can clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output are included for pulsed systems.

Texas Instruments ADC12QJ1600-SP Quad Channel ADC features a JESD204C serialized interface to reduce the amount of printed circuit board (PCB) routing, decreasing system size. Applications include satellite communications (SATCOM) and electronic warfare such as signals intelligence (SIGINT) and electronic intelligence (ELINT).

Features

  • Radiation performance
    • 300krad (Si) total ionizing dose (TID)
    • 120MeV-cm2/mg single-event latch-up (SEL)
    • Single-event upset (SEU) immune registers
  • ADC core
    • 12-bit resolution
    • 1.6GSPS maximum sampling rate
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (-1dBFS)
    • SNR (100MHz): 57.4dBFS
    • ENOB (100MHz): 9.1 bits
    • SFDR (100MHz): 64dBc
    • -147dBFS noise floor (-20dBFS)
  • 800mVPP-DIFF full-scale input voltage
  • 6GHz full-power input bandwidth
  • JESD204C serial data interface:
    • Support for 2 to 8 total SerDes lanes
    • 17.16Gbps maximum baud rate
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2GHz to 8.2GHz)
  • SYSREF windowing eases synchronization
  • 4 clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • 1.9W power consumption at 1GSPS
  • 1.1V, 1.9V power supply

Applications

  • Electronic warfare (SIGINT, ELINT)
  • SATCOM

Block Diagram

Texas Instruments ADC12QJ1600-SP Quad Channel ADC
Publicerad: 2022-11-30 | Uppdaterad: 2024-03-11