Infineon Technologies S25FL128S NOR Flash Memory Devices
Infineon Technologies S25FL128S FL-S NOR Flash Memory Devices are a 2.7V to 3.6V / 1.65V to 3.6V VIO Volt non-volatile memory using 65nm MIRRORBIT™ technology. Designed using the Eclipse architecture with a Page Programming Buffer, the 128-Mb S25FL128S FL-S NOR allows users to program up to 128 words (256 bytes) in one operation, resulting in faster effective programming and erase than prior generation SPI program or erase algorithms. The device connects to a host system via a Serial Peripheral Interface (SPI) and supports traditional SPI single-bit serial input and output (Single I/O or SIO), optional two-bit (Dual I/O or DIO), and four-bit (Quad I/O or QIO) serial commands.
As part of the FL-S family, S25FL128S FL-S NOR provides support for Double Data Rate (DDR) read commands for SIO, DIO, and QIO that transfer address and read data on both edges of the clock. Using FL-S devices at the supported higher clock rates with QIO or DDR-QIO commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR flash memories while reducing signal count dramatically. S25FL128S FL-S NOR offers high-density performance capabilities coupled with the flexibility and speed required by various embedded applications. Infineon Technologies S25FL128S FL-S NOR is ideal for code shadowing, XIP, and data storage.
Features
- CMOS 3.0 volt core with versatile I/O
- Serial peripheral interface (SPI) with multi-I/O
- SPI clock polarity and phase modes 0 and 3
- Double Data Rate (DDR) option
- Extended addressing of 24- or 32-bit address options
- Serial command set and footprint compatible with S25FL-A, S25FL-K, and S25FL-P SPI families
- Multi I/O command set and footprint compatible with S25FL-P SPI family
- READ commands
- Normal, fast, dual, quad, fast DDR, dual DDR, quad DDR
- AutoBoot - power up or reset and execute a Normal or Quad read command automatically at a preselected address
- Common Flash Interface (CFI) data for configuration information
- Programming (1.5 Mbytes/s)
- 256 or 512 Byte Page Programming buffer options
- Quad-Input Page Programming (QPP) for slow clock systems
- Automatic ECC -internal hardware error correction code generation with single bit error correction
- Erase (0.5 to 0.65 Mbytes/s)
- Hybrid sector size option of physical set of thirty two 4-kbyte sectors at top or bottom of address space with all remaining sectors of 64 kbytes, for compatibility with prior generation S25FL devices
- Uniform sector option - always erase 256-kbyte blocks for software compatibility with higher density and future devices
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