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Altera FPGA AI Suite

Altera FPGA AI Suite is a comprehensive development platform designed to streamline the creation of AI inference solutions on FPGAs. The platform integrates seamlessly with popular AI frameworks like TensorFlow and PyTorch, as well as the OpenVINO toolkit, enabling efficient model optimization and deployment. The suite leverages Intel® Quartus Prime Software to facilitate the integration of AI inference IP into FPGA designs, ensuring high performance and low latency. Additionally, it supports a wide range of pre-trained models from the Open Model Zoo, allowing for quick and easy model conversion and deployment. This makes the Altera FPGA AI Suite an ideal choice for developers looking to harness the power of FPGAs for AI applications in fields such as telecommunications, data centers, and industrial automation.

Features

  • High performance - Agilex™ 7 FPGA M-Series can achieve a maximum theoretical performance of 88.5 INT8 TOPS, or 3679 Resnet-50 frames per second at 90% FPGA utilization.
  • Low total cost of ownership with easy system integration - integrate AI IP with other system-level components to achieve a smaller footprint, lower power, and latency.
  • AI front-end support - use an AI front end such as TensorFlow, Caffe, Pytorch, MXNet, Keras, and ONNX.
  • Simple and standard flows - Create and add AI inference IP to current or emerging FPGA designs with Quartus Prime Software or Platform Designer.
  • Access to pre-trained models - FPGA AI Suite supports most of the models in the Open Model Zoo.
  • Seamless pre-trained model conversion - OpenVINO Toolkit converts models from most of the standard frameworks to intermediate representations.
  • Push-button optimized AI IP generation - seamlessly generates optimal AI inference IP from pre-trained AI models sweeping the design space for optimal resources to performance targets.
  • Hardware-less early model validation - Bit-accurate software emulation of the AI inference IP is available through the OpenVINO plugin interface, enabling quicker evaluation of the accuracy of the model without hardware.

Applications

  • Computer vision
  • Medical imaging and diagnosis
  • Industrial
  • Data centers
  • Industrial automation
  • Telecommunications 
  • Military
  • Braodcast

Inference Development Flow

The development flow seamlessly combines a hardware and software workflow into a generic end-to-end AI workflow. The steps are as follows:

1. OpenVINO Model Optimizer converts your pre-trained model to intermediate representation network files (.xml) and weights, biases files (.bin).

2. FPGA AI Suite compiler is used to:

- Provide estimated area or performance metrics for a given architecture file or produce an optimized architecture file. (Architecture refers to inference IP parameters such as size of PE array, precisions, activation functions, interface widths, window sizes, etc.)

- Compile network files into a .bin file with network partitions for FPGA and CPU (or both), along with weights and biases.

3. The compiled .bin file is imported by the user inference application at runtime. Runtime application programming interfaces (APIs) include Inference Engine API (runtime partition CPU and FPGA, schedule inference) and FPGA AI (DDR memory, FPGA hardware blocks).

4. Reference designs are available to demonstrate the basic operations of importing .bin and running inference on FPGA with supporting host CPUs (x86 and Arm® processors) as well as hostless inference operations.

5. Software emulation of the FPGA AI Suite IP is accessible through the OpenVINO plugin interface, enabling quicker evaluation of the accuracy of FPGA AI IP without access to hardware (available for Agilex™ 5 FPGA only).

Mechanical Drawing - Altera FPGA AI Suite
Mechanical Drawing - Altera FPGA AI Suite
Mechanical Drawing - Altera FPGA AI Suite

Videos

Design Guides

Supported FPGAs

Altera Agilex™ 5 FPGAs & SoCs

Mid-range FPGAs are optimized for high performance, low power, and small packages.

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Altera Stratix® 10 FPGA & SoC FPGA

Significantly improve performance, power efficiency, density, and system integration.

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Altera Arria® 10 GX FPGAs

Feature 96 full-duplex transceivers, supporting data rates of 17.4Gbps chip-to-chip.

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Altera Cyclone 10 FPGA:er

Leverera kostnads- och energibesparingar jämfört med tidigare generationers FPGA:er från Cyclone.

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Design Software

Altera Quartus® Prime Design Software

Multi-platform design environment for all phases of FPGA and CPLD design.

Learn Moreom Altera Quartus® Prime Design Software View Productsrelaterat till Altera Quartus® Prime Design Software
Publicerad: 2025-03-31 | Uppdaterad: 2025-04-14